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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7724 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual cmos - modulators functional block diagram avin(+) avin(? bvin(+) bvin(? mzero gc bip stby reset dvdd dvdd1 dgnd avdd agnd adata sclk bdata xtal off xtal1 xtal2/mclk dval ref1 ref2a ref2b clock circuitry AD7724 2.5v reference - modulator a - modulator b control logic features 13 mhz master clock frequency 0 v to +2.5 v or 1.25 v input range single bit output stream 90 db dynamic range power supplies avdd, dvdd: 5 v 5% dvdd1: 3 v 5% logic outputs 3 v/5 v compatible on-chip 2.5 v voltage reference 48-lead lqfp general description this device consists of two seventh order sigma-delta modula- tors. each modulator converts its analog input signal into a high speed 1-bit data stream. the part operates from a 5 v power supply and accepts a differential input range of 0 v to +2.5 v or 1.25 v centered about a common-mode bias. the analog inputs are continuously sampled by the analog modulators, eliminating the need for external sample-and-hold circuitry. the input information is contained in the output stream as a density of ones. the original information can be digitally reconstructed with an appropriate digital filter. the part provides an accurate on-chip 2.5 v reference for each modulator. a reference input/output function is provided to allow either the internal reference or an external system refer- ence to be used as the reference source for the modulator. the device is offered in a 48-lead lqfp package and designed to operate from C40 c to +85 c.
rev. b C2C AD7724Cspecifications 1 (avdd = 5 v 5%; dvdd = 5 v 5%, dvdd1 = 3 v 5%; agnd = dgnd = 0 v, f mclk = 13 mhz ac-coupled sine wave, ref2a = ref2b = 2.5 v; t a = t min to t max , unless otherwise noted.) parameter a version unit test conditions/comments static performance when tested with ideal fir filter as in figure 1 integral nonlinearity 0.003 % fsr typ offset error 0.24 % fsr typ gain error 2 0.6 % fsr typ offset error drift 37.69 v/ c typ gain error drift ref2 is an ideal reference, ref1 = agnd unipolar mode 37.69 v/ c typ bipolar mode 18.85 v/ c typ analog inputs signal input span (vin(+) C vin(C)) bipolar mode v ref2 /2 v max bip = v ih unipolar mode 0 to v ref2 v max bip = v il maximum input voltage avdd v minimum input voltage 0 v input sampling capacitance 2 pf typ input sampling rate 2 f mclk mhz differential input impedance 10 9 /(8 f mclk )k ? typ reference inputs ref1 output voltage 2.32 to 2.68 v min/max ref1 output voltage drift 60 ppm/ c typ ref1 output impedance 4 k ? typ reference buffer offset voltage 12 mv max offset between ref1 and ref2 using internal reference ref2 output voltage 2.32 to 2.68 v min/max ref2 output voltage drift 60 ppm/ c typ using external reference ref1 = agnd ref2 input impedance 10 9 /(16 f mclk )k ? typ external reference voltage range 2.32 to 2.68 v min/max applied to ref1 or ref2 dynamic specifications 3 when tested with ideal fir filter as in figure 1 bipolar mode bip = v ih , v cm = 2.5 v, vin(+) = vin(C) = 1.25 v p-p or vin(C) = 1.25 v, vin(+) = 0 v to 2.5 v signal-to-(noise + distortion) 90 db typ input bw = 0 khzC94.25 khz 86 db min total harmonic distortion C90 db max input bw = 0 khzC94.25 khz spurious free dynamic range C90 db max input bw = 0 khzC94.25 khz unipolar mode bip = v il , vin(C) = 0 v, vin(+) = 0 v to 2.5 v signal-to-(noise + distortion) 88 db typ input bw = 0 khzC94.25 khz total harmonic distortion C90 db typ input bw = 0 khzC101.556 khz spurious free dynamic range C90 db typ input bw = 0 khzC101.556 khz intermodulation distortion C93 db typ ac cmrr 96 db typ vin(+) = vin(C) = 2.5 v p-p, v cm = 1.25 v to 3.75 v, 20 khz clock square wave 4 mclk duty ratio 45 to 55 % max for specified operation v mclkh , mclk high voltage 4 v min mclk uses cmos logic v mclkl , mclk low voltage 0.4 v max sine wave xtal1 voltage swing 0.4 v p-p min xtal_off tied low 4 v p-p max logic inputs v ih , input high voltage 2.4 v min v il , input low voltage 0.8 v max i inh , input current 10 a max c in , input capacitance 10 pf max
rev. b C3C AD7724 parameter a version unit test conditions/comments logic outputs v oh , output high voltage dvdd1 C 0.2 v min |i out | 200 a v ol , output low voltage 0.4 v max |i out | 1.6 ma power supplies avdd/dvdd 4.75/5.25 v min/v max dvdd1 2.85/5.25 v min/v max i dd (total for avdd, dvdd) digital inputs equal to 0 v or dvdd active mode 60 ma max standby mode 20 a max notes 1 operating temperature range is as follows: a version: C40 c to +85 c. 2 gain error excludes reference error. the modulator gain is calibrated wrt the voltage on the ref2 pin. 3 measurement bandwidth = 0.5 f mclk ; input level = C0.05 db. 4 when a square wave clock is used, the dynamic specifications will degrade by 1 db typically. specifications subject to change without notice. bit stream 94.25khz filter 1 120db 304.687khz bandwidth = 94.25khz transition = 304.687khz attenuation = 120db coefficients = 384 decimate by 32 filter 2 16-bit output 94.25khz 90db 108.874khz bandwidth = 94.25khz transition = 108.874khz attenuation = 90db coefficients = 151 decimate by 2 figure 1. digital filter (consists of two fir filters). this filter is implemented on the ad7722.
rev. b AD7724 C4C timing characteristics 1, 2 limit at t min , t max parameter (a version) unit conditions/comments f mclk 100 khz min master clock frequency 15 mhz max 13 mhz for specified performance t delay 14 ns max mclk to sclk delay t 1 67 ns min master clock period t 2 0.45 t mclk ns min master clock input high time t 3 0.45 t mclk ns min master clock input low time t 4 15 ns min data hold time after sclk rising edge t 5 10 ns min reset pulsewidth t 6 10 ns min reset low time before mclk rising t 7 20 t mclk ns max dval high delay after reset low t 8 3 ns max data access time after sclk falling edge t 9 t 3 Ct 8 ns max data valid time before sclk rising edge notes 1 sample tested at 25 c to ensure compliance. 2 guaranteed by design. to output pin c l 50pf i oh 200 a i ol 1.6ma 1.6v figure 2. load circuit for access time and bus relinquish time t 4 sclk (o) data (o) t 1 t 2 t 3 note: o signifies an output t 8 t 9 figure 3. data timing t 5 mclk (i) reset (i) dval (o) t 6 t 7 note: i signifies an input o signifies an output figure 4. reset timing (avdd = 5 v 5%; dvdd = 5 v 5%; dvdd1 = 3 v 5%; agnd = dgnd = 0 v, ref2a = ref2b = 2.5 v, unless otherwise noted.)
rev. b AD7724 C5C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7724 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * (t a = 25 c unless otherwise noted) dvdd to dgnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v avdd to agnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v avdd to dvdd . . . . . . . . . . . . . . . . . . . . . . . C1 v to +1 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v digital inputs to dgnd . . . . . . . . C0.3 v to dvdd + 0.3 v digital outputs to dgnd . . . . . . . C0.3 v to dvdd + 0.3 v vin(+), vin(C) to agnd . . . . . . . C0.3 v to avdd + 0.3 v ref1 to agnd . . . . . . . . . . . . . . . C0.3 v to avdd + 0.3 v ref2 to agnd . . . . . . . . . . . . . . . C0.3 v to avdd + 0.3 v refin to agnd . . . . . . . . . . . . . . C0.3 v to avdd + 0.3 v operating temperature range . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) avdd agnd bvin( ) nc bvin(+) agnd avdd avdd agnd avin( ) nc avin(+) agnd avdd nc = no connect nc stby mzero reset nc gc bip xtal_off AD7724 nc nc nc nc agnd ref2a agnd ref1 avdd nc ref2b agnd nc nc nc xtal1 xtal1/mclk dvdd dgnd dgnd adata bdata sclk dvdd1 dval nc ordering guide temperature package package model range description option AD7724ast C40 c to +85 c 48-lead plastic thin quad flatpack (lqfp) st-48
rev. b AD7724 C6C pin function descriptions mnemonic description avdd analog positive supply voltage, 5 v 5%. agnd ground reference point for analog circuitry. avin(C), avin(+) a nalog input to modulator a. in unipolar operation, the analog input range on avin(+) is avin(C) to (avin(C) + vref); for bipolar operation, the analog input range on avin(+) is (avin(C) vref/2). the absolute analog input range must lie between 0 and avdd. the input range is continuously sampled and pro- cessed by the analog modulator. stby standby, logic input. when stby is high, the device is placed in a low power mode. when stby is low, the device is powered up. mzero digital control input. when mzero is high, the modulator inputs are internally grounded i.e. tied to agnd in unipolar mode and ref2 in bipolar mode. mzero allows on-chip offsets to be calibrated out. mzero is low for normal operation. reset reset logic input. reset is an asynchronous input. when reset is taken high, the sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. dval goes low for 20 mclk cycles while the modulator is being reset. xtal1 input to crystal oscillator amplifier. this pin can also be used to gain up a small input square or sine wave with xtal_off tied low (see figure 32 on page 12). when a clock source is applied to xtal1, sclk will be inverted and the xtal1_clk to sclk delay will be typically 14 ns longer than t delay . xtal2/mclk clock input. an external clock source can be applied directly to this pin with xtal_off tied high. in this case, xtal1 should be tied to agnd. alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 m ? resistor, can be connected between xtal1 and xtal2 with xtal_off tied low. exter- nal capacitors are then required from the xtal1 and xtal2 pins to ground. consult the crystal manufacturer's recommendation for the load capacitors. a sine wave can also be used to provide the clock. a sine wave with a voltage swing between 0.4 v p-p and 4 v p-p is needed. xtal_off is tied low and a 1 m ? resistor is needed between xtal1 and xtal2. a 22 pf capacitor is connected in parallel with this resistor. the sine wave is ac coupled to xtal1 using a 120 pf capacitor. the use of a sine wave to generate the clock eliminates the need for a square wave clock source which introduces noise. dvdd digital supply voltage, 5 v 5%. dgnd ground reference for the digital circuitry. adata modulator a bit stream. the digital bit stream from the sigma-delta modulator is output at adata. bdata modulator b bit stream. the digital bit stream from the sigma-delta modulator is output at bdata. sclk serial clock, logic output. the bit stream from modulator a and modulator b is valid on the rising edge of asclk. dvdd1 digital supply voltage for the digital outputs. dvdd1 can have a value of 5 v 5% or 3 v 5% so that the logic outputs can be 3 v or 5 v compatible. dval data valid logic output. a logic high on dval indicates that the data bit stream from the AD7724 is an accurate digital representation of the analog voltage at the input to the sigma-delta modulator. the dval pin is set low for 20 mclk cycles if the analog input is overranged. xtal_off oscillator enable input. a logic high disables the crystal oscillator amplifier to allow use of an external clock source. xtal_off is set to a logic low when an external crystal is used between xtal1 and xtal2. bip analog input range select, logic input. a logic low on this input selects unipolar mode. a logic high selects bipolar mode. gc digital control input. when gc is high, the gain error of the modulator can be calibrated. bvin(C), bvin(+) analog input to modulator b. in unipolar operation, the analog input range on bvin(+) is bvin(C) to (bvin(C) + vref); for bipolar operation, the analog input range on bvin(+) is (bvin(C) vref/2). the absolute analog input range must lie between 0 and avdd. the input range is continuously sampled and pro- cessed by the analog modulator. ref2b reference input/output to sigma-delta modulator b. ref2b connects to the output of an external buffer amplifier used to drive sigma-delta modulator b. when ref2b is used as an input, ref1 must be connected to agnd. ref1 reference input/output. ref1 connects through 3 k ? to the output of the internal 2.5 v reference and to the input of two buffer amplifiers that drive - ? modulator a and - ? modulator b. the pin can be overdriven with an external 2.5 v reference. ref2a reference input/output to sigma-delta modulator a. ref2a connects to the output of an external buffer amplifier used to drive sigma-delta modulator a. when ref2a is used as an input, ref1 must be connected to agnd.
rev. b AD7724 C7C terminology (ideal fir filter used with AD7724 [figure 1]) integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale (not to be con- fused with bipolar zero), a point 0.5 lsb below the first code transition (10 0...00 to 100...01 in bipolar mode and 000...00 to 000...01 in unipolar mode) and full scale, a point 0.5 lsb above the last code transition (01 1...10 to 011...11 in bipolar mode and 11 1...10 to 111...11 in unipolar mode). the error is expressed in lsbs. common-mode rejection ratio the ability of a device to reject the effect of a voltage applied to both input terminals simultaneouslyoften through variation of a ground levelis specified as a commonCmode rejection ratio. cmrr is the ratio of gain for the differential signal to the gain for the common-mode signal. unipolar offset error unipolar offset error is the deviation of the first code transition from the ideal vin(+) voltage which is (vin(C) + 0.5 lsb) when operating in the unipolar mode. bipolar offset error this is the deviation of the midscale transition (11 1...11 to 000... 00) from the ideal vin(+) voltage which is (vin(C) C0.5 lsb) when operating in the bipolar mode. gain error the first code transition should occur at an analog value 1/2 lsb above minus full scale. the last code transition should occur for an analog value 1 1/2 lsb below the nominal full-scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-(noise + distortion) signal-to-(noise + distortion) is the measured signal-to-noise plus distortion ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise plus distortion is the rms sum of all of the nonfundamental signals and harmonics up to half the output data rate (f o /2), excluding dc. signal-to- (noise + distortion) is dependent on the number of quantiza- tion levels used in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for a sine wave input is given by signal-to- ( noise + distortion) = (6.02 n + 1.76) db where n is the number of bits. total harmonic distortion thd is the ratio of the rms sum of harmonics to the rms value of the fundamental. thd is defined as thd = 20 log ( v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 ) v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonic. spurious free dynamic range spurious free dynamic range is the difference, in db, between the peak spurious or harmonic component in the adc output spectrum (up to f o /2 and excluding dc) and the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the output spectrum of the fft. for input signals whose second harmonics occur in the stop band region of the digital filter, a spur in the noise floor limits the sfdr. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb).
rev. b AD7724 C8C (avdd = dvdd = 5.0 v, t a = 25 c; clkin = 13 mhz ac-coupled sine wave, ain = 20 khz, bipolar mode; v in (+) = 0 v to 2.5 v, v in (C) = 1.25 v unless otherwise noted) input level db db 110 100 50 40 30 0 20 10 90 80 70 60 sfdr s/ (n+d) tpc 1. s/(n+d) and sfdr vs. analog input level input frequency khz db 85 90 115 0 20 100 40 60 80 95 100 105 110 thd snr sfdr v in (+) = v in ( ) = 1.25v p-p v cm = 2.5v tpc 4. snr, thd, and sfdr vs. input frequency temperature c db 94 116 50 25 100 0255075 96 108 110 112 114 100 102 106 104 98 thd 3rd 4th 2nd tpc 7. thd vs. temperature Ctypical performance characteristics output data rate ksps db 84 92 85 88 89 90 91 86 87 0 50 300 100 150 200 250 ain = 1/5 bw tpc 2. s/(n+d) vs. output sample rate output data rate ksps db 84 92 85 88 89 90 91 86 87 0 50 300 100 150 200 250 ain = 1/5 bw v in (+) = v in ( ) = 1.25v p-p v cm = 2.5v tpc 5. s/(n+d) vs. output sample rate codes frequency of occurence 5000 0 n 3n 2 n+3 n 1 n n+1 n+2 4500 2000 1500 1000 500 4000 3500 2500 3000 v in (+) = v in ( ) clkin = 13mhz 8k samples tpc 8. histogram of output codes with dc input input frequency khz db 85 90 115 0 20 100 40 60 80 95 100 105 110 snr sfdr thd tpc 3. snr, thd, and sfdr vs. input frequency temperature c 92.0 91.5 88.0 50 0 100 50 90.0 89.5 88.5 89.0 91.0 90.5 db tpc 6. snr vs. temperature code dnl error lsb 1.0 0.8 1.0 0 20000 65535 40000 0.4 0.8 0.6 0 0.2 0.6 0.2 0.4 )4(8 !

rev. b AD7724 C9C 10 20 30 40 50 60 70 80 90 100 110 120 130 0 db 0 6.5 frequency mhz tpc 11. modulator output (0 hz to mclk/2) 0 154 db 20 80 100 120 140 40 60 0e+0 10e+3 20e+3 30e+3 40e+3 50e+3 60e+3 70e+3 80e+3 98e+3 clkin = 13mhz snr = 90.1db s/(n+d) = 89.2db sfdr = 99.5db thd = 96.6db 2nd = 100.9db 3rd = 106.0db 4th = 99.5db 90e+3 tpc 12. 16k point fft 0 154 db 20 80 100 120 140 40 60 0e+0 10e+3 20e+3 30e+3 40e+3 50e+3 60e+3 70e+3 80e+3 96e+3 90e+3 xtal = 12.288mhz snr = 89.0db s/(n+d) = 87.8db sfdr = 94.3db thd = 93.8db 2nd = 94.3db 3rd = 108.5db 4th = 105.7db tpc 13. 16k point fft code inl error lsb 1.0 0.8 1.0 0 20000 6 5535 40000 0.4 0.8 0.6 0 0.2 0.6 0.2 0.4 tpc 10. integral nonlinearity error 10 20 30 40 50 60 70 80 90 100 110 120 130 0 db 0 409.0268 frequency khz )4(&, 9

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,:8:#23 =;* 0 154 db 20 80 100 120 140 40 60 0e+0 10e+3 20e+3 30e+3 40e+3 50e+3 60e+3 70e+3 80e+3 98e+3 ain = 90khz clkin = 13mhz snr = 89.6db s/(n+d) = 89.6db sfdr = 108.0db 90e+3 tpc 15. 16k point fft 0 154 db 20 80 100 120 140 40 60 0e+0 10e+3 20e+3 30e+3 40e+3 50e+3 60e+3 70e+3 80e+3 96e+3 ain = 90khz xtal = 12.288mhz snr = 88.1db s/(n+d) = 88.1db sfdr = 103.7db 90e+3 tpc 16. 16k point fft
rev. b AD7724 C10C circuit description the AD7724 employs a sigma-delta conversion technique to convert the analog input into a digital pulse train. the analog input is continuously sampled by a switched capacitor modulator at twice the rate of the clock input frequency (2 f mclk ). the digital data that represents the analog input is in the ones den- sity of the bit stream at the output of the sigma-delta modulator. the modulator outputs the bit stream at a data rate equal to f mclk . due to the high oversampling rate, which spreads the quantiza- tion noise from 0 to f mclk /2, the noise energy contained in the band of interest is reduced (figure 5a). to reduce the quantiza- tion noise further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (figure 5b). band of interest f mclk /2 band of interest a. b. f mclk /2 quantization noise noise shaping figure 5. sigma-delta adc using the AD7724 adc differential inputs the AD7724 uses differential inputs to provide common-mode noise rejection (i.e., the converted result will correspond to the differential voltage between the two inputs). the absolute volt- age on both inputs must lie between agnd and avdd. in the unip olar mode, the full scale-input range (vin(+) C vin(C)) is 0 v to v ref . in the bipolar mode configuration, the full-scale analog input range is v ref /2. the bipolar mode allows com plementary input signals. alternatively, vin(C) can be connected to a dc bias voltage to allow a single-ended input on vin(+) equal to v bias v ref /2. differential inputs the analog input to the modulator is a switched capacitor design. the analog input is converted into charge by highly linear sam- pling capacitors. a simplified equivalent circuit diagram of the analog input is shown in figure 6. a signal source driving the analog input must be able to provide the charge onto the sam- pling capacitors every half mclk cycle and settle to the req uired accuracy within the next half cycle. a b a b 2pf 2pf ac ground 500 a b a b mclk vin(+) vin( ) 500 figure 6. analog input equivalent circuit since the AD7724 samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low differential mode noise at each input. the amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7724. when a capacitive load is sw itched onto the output of an op amp, the amplitude will momentarily drop. the op amp will try to correct the situation and, in the process, hits its slew rate limit. this nonlinear response, which can cause excessive ring- ing, can lead to distortion. to remedy the situation, a low-pass rc filter can be connected between the amplifier and the input to the AD7724 as shown in figure 7. the external capacitor at each input aids in supplying the current spikes created during the sampling process. the resistor in the diagram, as well as creating a pole for the antialiasing, isolates the op amp from the transient nature of the load. analog input r c vin(+) vin( ) r c figure 7. simple rc antialiasing circuit the differential input impedance of the AD7724 sw itched capaci- tor input varies as a function of the mclk frequency, given by the equation: zfk in mclk = () 10 8 9 / ? even though the voltage on the input sampling capacitors may not have enough time to settle to the accuracy indicated by the resolution of the AD7724, as long as the sampling capacitor charg- ing follows the exponential curve of rc circuits, only the gain accuracy suffers if the input capacitor is switched away too early.
rev. b AD7724 C11C an alternative circuit configuration for driving the differential inputs to the AD7724 is shown in figure 8. r 100 c 2.7nf vin(+) vin( ) c 2.7nf c 2.7nf r 100 figure 8. differential input with antialiasing a capacitor between the two input pins sources or sinks charge to allow most of the charge needed by one input to be effectively supplied by the other input. this minimizes undesirable charge transfer from the analog inputs to and from ground. the series resistor isolates the operational amplifier from the current spikes created during the sampling process and provides a pole for antialiasing. the 3 db cutoff frequency of the antialias filter is given by equation 1, and the attenuation of the filter is given by equation 2. frc db ext ext 3 12 = () / (1) attenuation f f db =+ () ? ? ? ? ? ? 20 1 1 3 2 log // (2) the choice of the filter cutoff frequency will depend on the amount of roll-off that is acceptable in the passband of the digi- tal filter and the required attenuation at the first image frequency. the capacitors used for the input antialiasing circuit must have low dielectric absorption to avoid distortion. film capacitors such as polypropylene or polycarbonate are suitable. if ceramic capacitors are used, they must have npo dielectric. applying the reference the reference circuitry used in the AD7724 includes an on-chip 2.5 v bandgap reference and a reference buffer circuit. the block diagram of the reference circuit is shown in figure 9. the internal reference voltage is connected to ref1 via a 3 k ? resis tor and is internally buffered to drive the analog modulators switched capacitor dac (ref2). when using the internal refer- ence, connect 110 nf between ref1 and agnd. if the internal reference is required to bias external circuits, use an external precision op amp to buffer ref1. 4k reference buffer 1v 2.5v reference switched-cap dac ref ref1 ref2 comparator 110nf figure 9. reference circuit block diagram the AD7724 can operate with its internal reference, or an external reference can be applied in two ways. an external reference can be connected to ref1, overdriving the internal reference. however, an error will be introduced due to the offset of the internal buffer amplifier. for lowest system gain errors when using an external reference, ref1 is grounded (disabling the in ternal buffer) and the external reference is con- nected to ref2. in all cases, since the ref2 voltage connects to the analog modu- lator, a 110 nf capacitor must connect directly from ref2 to agnd. the external capacitor provides the charge required for the dynamic load presented at the ref2 pin (figure 10). a b b 4pf a b a b mclk ref2 a 4pf switched-cap dac ref 110nf figure 10. ref2 equivalent circuit the ad780 is ideal to use as an external reference with the AD7724. figure 11 shows a suggested connection diagram. ad780 1 2 3 4 8 7 6 5 nc +v in temp gnd o/p select nc v out trim 22nf 1 f ref2 22 f 110nf ref1 5v nc = no connect figure 11. external reference circuit connection
rev. b AD7724 C12C input circuits figures 12 and 13 show two simple circuits for bipolar mode operation. both circuits accept a single-ended bipolar signal source and create the necessary differential signals at the input to the adc. the circuit in figure 12 creates a 0 v to 2.5 v signal at the vin(+) pins to form a differential signal around an initial bias voltage of 1.25 v. for single-ended applications, best thd performance is obtained with vin(C) set to 1.25 v rather than 2.5 v. the input to the AD7724 can also be driven differen- tially with a complementary input as shown in figure 13. in this case, the input common-mode voltage is set to 2.5 v. the 2.5 v p-p full-scale differential input is obtained with a 1.25 v p-p signal at each input in antiphase. this configuration minimizes the required output swing from the amplifier circuit and is useful for single supply applications. 12pf 1k 1k 1/2 op275 ain = 1.25v + 12pf 1k 110nf r 1nf vin( ) vin(+) ref1 ref2 110nf differential input = 2.5v p-p vin( ) bias voltage = 2.5v op07 r 1nf + 1/2 op275 + 1k figure 12. single-ended analog input for bipolar mode operation 12pf 1k ain = 0.625v 1k 1k 12pf 1k 1/2 op275 110nf r r 1nf vin( ) 1nf 1/2 op275 vin(+) differential input = 2.5v p-p common-mode voltage = 2.5v ref1 op07 ref2 110nf figure 13. single-ended-to-differential analog input circuit for bipolar mode operation the 1 nf capacitors at each input store charge to aid the amplifier settling as the input is continuously switched. a resistor in series with the drive amplifier output and the 1 nf input capacitor may also be used to create an antialias filter. clock generation the AD7724 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the adc. the connection diagram for use with the crystal is shown in figure 14. consult the crystal manufacturers recommenda- tion for the load capacitors. 1m xtal mclk figure 14. crystal oscillator connection an external clock must be free of ringing and have a minimum rise time of 5 ns. degradation in performance can result as high edge rates increase coupling that can generate noise in the sam- pling process. the connection diagram for an external clock source (figure 15) shows a series damping resistor connected between the clock output and the clock input to the AD7724. the optimum resistor will depend on the board layout and the impedance of the trace connecting to the clock input. clock circuitry mclk 25 150 figure 15. external clock oscillator connection a low phase clock should be used to generate the adc sam- pling clock because sampling clock jitter effectively modulates the input signal and raises the noise floor. the sampling clock generator should be isolated from noisy digital circuits, grounded and heavily decoupled to the analog ground plane. a sine wave can also be used to provide the clock (figure 16.) a sine wave with a voltage swing between 0.4 v p-p and 4 v p-p is needed. xtal_off is tied low and a 1 m ? resistor is needed between xtal1 and xtal2. a 22 pf capacitor is connected in parallel with this resistor. the sine wave is ac coupled to xtal1 using a 120 pf capacitor. the use of a sine wave to generate the clock elimin ates the need for a square wave clock source which introduces noise. 1m xtal1 xtal2 xtal_off 22pf sinewave input 120pf figure 16. using a sine wave input as a clock source
rev. b AD7724 C13C the sampling clock generator should be referenced to the ana- log ground plane in a split ground system. however, this is not always possible because of system constraints. in many cases, the sampling clock must be derived from a higher frequency multipurpose system clock that is generated on the digital ground plane. if the clock signal is passed between its origin on a digital plane to the AD7724 on the analog ground plane, the ground noise between the two planes adds directly to the clock and will produce excess jitter. the jitter can cause unwanted degradation in the signal-to-noise ratio and also produce unwanted harmonics. this can be somewhat remedied by transmitting the sampling signal as a differential one, using either a small rf transformer or a high-speed differential driver and receiver such as pecl. in either case, the original master system clock should be generated from a low phase noise crystal oscillator. offset and gain calibration the analog inputs of the AD7724 can be configured to measure offset and gain errors. pins mzero and gc are used to config- ure the part. before calibrating the device, the part should be reset so that the modulator is in a known state at calibration. when mzero is taken high, the analog inputs are tied to agnd in unipolar mode and vref in bipolar mode. after taking mzero high, 1000 mclk cycles should be allowed for the circuitry to settle before the bit stream is read from the device. the ideal ones density is 50% when bipolar operation is selected and 37.5% when unipolar mode is selected. when gc is taken high, vin(C) is tied to ground while vin(+) is tied to vref. again, 1000 mclk cycles should be allowed for the circuitry to settle before the bit stream is read. the ideal ones density is 62.5%. the calibration results apply only for the particular analog input mode (unipolar/bipolar) selected when performing the calibra- tion cycle. on changing to a different analog input mode, a new calibration must be performed. before calibrating, ensure that the supplies have settled and that the voltage on the analog input pins is between the supply voltages. standby the part can be put into a low power standby mode by taking stby high. during standby, the clock to the modulators is turned off and bias is removed from all analog circuits. reset the reset pin is used to reset the modulators to a known state. when reset is taken high, the integrator capacitors of the modulator are shorted and dval goes low and remains low until 20 mclk cycles after reset is deasserted. however, an additional 1000 mclk cycles should be allowed before reading the modulator bit stream as the modulator circuitry needs to settle after the reset. dval the dval pin is used to indicate that an overrange input signal has resulted in invalid data at the modulator output. as with all single-bit dac high-order sigma-delta modulators, large over- loads on the inputs can cause the modulator to go unstable. the modulator is designed to be stable with signals within the input bandwidth that exceed full-scale by 100%. when instability is detected by internal circuits, the modulator is reset to a stable state and dval is held low for 20 clock cycles. grounding and layout since the analog inputs are differential, most of the voltages in the analog modulator are common-mode voltages. the excel- lent common-mode rejection of the part will remove common- mode noise on these inputs. the analog and digital supplies to the AD7724 are independent and separately pinned out to mini- mize coupling between analog and digital sections of the device. the printed circuit board that houses the AD7724 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it g ives the best shielding. digital and analog ground planes should be joined in only one place. if the AD7724 is the only device requiring an agnd-to-dgnd connection, the ground planes should be connected at the agnd and dgnd pins of the AD7724. if the AD7724 is in a system where multiple devices require agnd-to-dgnd connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7724. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7724 to avoid noise coupling. the power supply lines to the AD7724 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. good decoupling is important when using high resolution adcs. all analog and digital supplies should be decoupled to agnd and dgnd respectively, with 100 nf ceramic capaci- tors in parallel with 10 f tantalum capacitors. to achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. in systems where a common supply voltage is used to drive both the avdd and dvdd of the AD7724, it is recom- mended that the systems avdd supply be used. this supply should have the recommended analog supply decoupling between the avdd pins of the AD7724 and agnd and the recom- mended digital supply decoupling between the dvdd pins and dgnd.
rev. b AD7724 C14C 48-lead plastic thin quad flatpack (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max seating plane 0.030 (0.75) 0.018 (0.45) 0.006 (0.15) 0.002 (0.05) 0.007 (0.18) 0.004 (0.09) 0 min 7 0 0.057 (1.45) 0.053 (1.35) outline dimensions dimensions shown in inches and (mm).
rev. b C15C AD7724 revision history location page data sheet changed from rev. a to rev. b. additions to timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
C16C c01187C0C3/02(b) printed in u.s.a.

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